Mode 2 & 0
| Start
|
End
|
Area
|
Size (Bytes)
|
| 0x0000 |
0x003F |
RAM - Registers |
63
|
| 0x0040 |
0x0056 |
RAM - "Battery backed up" |
22
|
| 0x0057 |
0x01BF |
RAM |
360
|
| 0x0000 |
0x01BF |
RAM - All |
448
|
| 0x0040 |
0x01BF |
RAM - Usable |
383
|
| 0x01BF |
0x8000 |
THE VOID |
32,321
|
| 0x8000 |
0xFFFF |
ROM - External |
32,768 (32KB)
|
| 0xD000 |
0xFFFF |
ROM - Internal (Mode 0) |
12,288 (12KB)
|
| 0xFFE0 |
0xFFFF |
ROM - Vector Table |
31
|
RAM
Registers
0x0000 - 0x003F
| Address
|
Name
|
Description
|
| 0x0000 |
DDRA |
Port A Data Direction Register
|
| 0x0001 |
DDRB |
Port B Data Direction Register
|
| 0x0002 |
PORTA |
Port A
|
| 0x0003 |
PORTB |
Port B
|
| 0x0004 |
DDRC |
Port C Data Direction Register
|
| 0x0005 |
DDRD |
Port D Data Direction Register
|
| 0x0006 |
PORTC |
Port C
|
| 0x0007 |
PORTD |
Port D
|
| 0x0008 |
T1_CSR |
Timer 1 Control Status Register
|
| 0x0009:0x000A |
T1T2_CLK |
Timer 1 & 2 free running counter
|
| 0x000B:0x000C |
T1_OCR |
Timer 1 Output Compare Register
|
| 0x000D:0x000E |
T1_ICR |
Timer 1 Input Capture Register
|
| 0x000F |
PORTC_SCR |
Port C status and control register
|
| 0x0010 |
SCI_BAUD |
Serial communication rate and mode control register
|
| 0x0011 |
SCI_SCR |
Serial communication status and control register
|
| 0x0012 |
SCI_RX |
SCI data read register
|
| 0x0013 |
SCI_TX |
SCI data write register
|
| 0x0014 |
RAM_CTL |
RAM control register / battery saving status register
|
| 0x0015 |
DDRE |
Port E Direction Register
|
| 0x0016 |
PORTE |
Port E
|
| 0x0017 |
|
|
| 0x0018 |
T2_CSR |
Timer 2 Control Status Register
|
| 0x0019:0x001A |
T3_CSR |
Timer 3 Control Status Register
|
| 0x001B:0x001C |
T2_OCR |
Timer 2 Output Compare Register
|
| 0x001D:0x001E |
T2_ICR |
Timer 2 Input Capture Register
|
| 0x001F |
ADC_CTL |
Analog-Digital Converter Control Register
|
| 0x0020 |
ADC_DATA |
Analog-Digital Converter Data
|
| 0x0021 |
|
| 0x0022 |
|
| 0x0023 |
|
| 0x0024 |
PA_CTL |
Pulse accumulator Control Register
|
| 0x0025 |
PA_CNT |
Pulse accumulator Counter
|
| 0x0026 |
RTI_CTL |
Real Time Interrupt Control Register
|
| 0x0027 |
RTI_FREQ |
Real Time Interrupt Frequency
|
| 0x0028 |
Skipped?
|
| 0x0029:0x002A |
T3_clock1 |
Timer 3 Readable counter 1
|
| 0x002B:0x002C |
T3_OCR |
Timer 3 Output Compare Register
|
| 0x002D:0x002E |
T3_clock2 |
Timer 3 Readable counter 2
|
| 0x002F |
PORTF |
Port F
|
| 0x0030 |
CONF_RES |
Stores status of configuration resistors
|
| 0x0031 |
|
|
| 0x0032 |
|
|
| 0x0033 |
|
|
| 0x0034 |
|
|
| 0x0035 |
|
|
| 0x0036 |
|
|
| 0x0037 |
|
|
| 0x0038 |
|
|
| 0x0039 |
|
|
| 0x003A |
|
|
| 0x003B |
|
|
| 0x003C |
|
|
| 0x003D |
|
|
| 0x003E |
|
|
| 0x003F |
|
|
Memory
0x0040 - 0x01BF*
- The stack is usually placed at the top of RAM (0x01BF)
ROM
0x8000 - 0xFFFF External (Mode 2)
0xD000 - 0xFFFF Internal (Mode 0)
Interrupt Vector Table
0xFFE0 - 0xFFFF
| Address
|
Description
|
| 0xFFE0-0FFE1 |
Serial Rx Interrupt
|
| 0xFFE2-0xFFE3 |
(Soft reset)
|
| 0xFFE4-0xFFE5 |
Real-time Interrupt
|
| 0xFFE6-0xFFE7 |
(Soft reset)
|
| 0xFFE8-0xFFE9 |
(Soft reset)
|
| 0xFFEA-0xFFEB |
(Soft reset)
|
| 0xFFEC-0xFFED |
Output Compare Interrupt 3
|
| 0xFFEE-0xFFEF |
Output Compare Interrupt 2
|
| 0xFFF0-0xFFF1 |
Output Compare Interrupt 1
|
| 0xFFF2-0xFFF3 |
(Soft reset)
|
| 0xFFF4-0xFFF5 |
Input Capture Interrupt 2
|
| 0xFFF6-0xFFF7 |
Input Capture Interrupt 1
|
| 0xFFF8-0xFFF9 |
(Soft reset)
|
| 0xFFFA-0xFFFB |
(Soft reset)
|
| 0xFFFC-0xFFFD |
Failure Interrupt
|
| 0xFFFE-0xFFFF |
System Reset
|